The specification defines two primary methods for transmitting data to a display:
+------------------------------------------------------------+ | HOST PROCESSOR | | +------------------------------------------------------+ | | | Application Layer | | | +------------------------------------------------------+ | | | Protocol Layer (DCS / Packet Routing) | | | +------------------------------------------------------+ | | | Lane Management Layer | | | +------------------------------------------------------+ | | | PHY Layer (D-PHY) | | | +------------------------------------------------------+ | +------------------------------------------------------------+ || Clock Lane + 1 to 4 Data Lanes || +------------------------------------------------------------+ | PERIPHERAL DEVICE | | +------------------------------------------------------+ | | | PHY Layer (D-PHY) | | | +------------------------------------------------------+ | | | Lane Management Layer | | | +------------------------------------------------------+ | | | Protocol Layer (DCS / Packet Routing) | | | +------------------------------------------------------+ | | | Display Module | | | +------------------------------------------------------+ | +------------------------------------------------------------+ Lane Configurations
, supports even higher resolutions (up to 4K and 8K) and integrates with the MIPI VESA V-DC-M Display Stream Compression (DSC) mipi dsi specification pdf
Contains the command parameters or short data payloads.
C-PHY was introduced in later revisions of the specification to provide higher throughput over fewer pins. From a system or software perspective, the serialization
The specification includes critical sections covering video mode timing parameters, command mode packet structures, and CRC-16 error detection for display data.
From a system or software perspective, the serialization and deserialization operations should be transparent. However, the transformation to serial data and back to parallel introduces increased latency for transactions requiring a response from the peripheral. For example, reading a pixel from a frame buffer has higher latency using DSI compared to DBI. From a system or software perspective
Uses low-voltage differential signaling (typically 200mV) for fast data and video transmission. Data rates can exceed several gigabits per second per lane.
Understanding the evolution of the MIPI DSI specification is essential for selecting the right version for your project. Here's a summary of the major versions and their key features: