Eyeq4 Datasheet ◉
Memory, I/O, and Sensor Interfaces
According to core system floorplans evaluated by TechInsights, the EyeQ4 computational architecture consists of 14 distinct processor cores divided into four core classes:
: Manufactured using STMicroelectronics' 28nm FD-SOI (Fully Depleted Silicon On Insulator) process, which is optimized for low power consumption.
A CGRA (Coarse Grained Reconfigurable Array) dataflow machine that provides fixed-function hardware density with software programmability. 4. MPC (Multi-threaded Processing Cluster) Quantity: 2 cores. eyeq4 datasheet
: Classifying every pixel in a video frame (e.g., identifying road vs. sidewalk vs. obstacles).
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6 cores dedicated to VLIW and SIMD operations, ideal for short integral types in vision algorithms. Multi-threaded Processor Cluster Memory, I/O, and Sensor Interfaces According to core
(Fully Depleted Silicon On Insulator) technology for low power consumption. Vision Processing : Supports visual input from up to simultaneously at 30fps. Yole Group Key Functional Features Environment Modeling
Automotive Grade: -20°C to +85°C (Extended Storage up to +105°C) Mobileye EyeQ4 Vision Processor Family - Yole Group
: Includes support for complex path planning and "Driving Policy" to manage vehicle behavior in traffic. Yole Group Product Variants EyeQ4-High MPC (Multi-threaded Processing Cluster) Quantity: 2 cores
The EyeQ4 datasheet is more than a technical list; it is a blueprint for the "eyes" of the modern vehicle. By balancing high-speed visual processing with rigorous safety standards and low power consumption, Mobileye created a platform that transitioned autonomous driving from a laboratory concept into a scalable, everyday reality for millions of drivers. (like TOPS) or compare it to the newer EyeQ5/EyeQ6
Unlike earlier systems limited to front-only detection, the EyeQ4 can identify vehicles and obstacles from various angles using 360-degree vision.
A wide vector machine (VLIW and SIMD) optimized for computer vision and deep learning algorithms. 3. PMA (Programmable Macro Array) Quantity: 2 cores.
: Multiple lanes allowing direct interfacing with high-resolution CMOS image sensors.
: A cost-optimized variant with a subset of cores, typically used for monocular or trifocal camera configurations in standard ADAS applications. Key Interfaces and Connectivity